Nehalem (microarchitecture)
Logo for Core i7 Bloomfield processors | |
| General information | |
|---|---|
| Launched | November 11, 2008 |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer |
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| Performance | |
| Max. CPU clock rate | 1.06 GHz to 3.33 GHz |
| QPI speeds | 4.80 GT/s to 6.40 GT/s |
| DMI speeds | 2 GT/s |
| Physical specifications | |
| Transistors |
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| Cores |
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| Sockets | |
| Cache | |
| L1 cache | 64 KB per core (32 KB data + 32 KB instructions) |
| L2 cache | 256 KB per core |
| L3 cache | 2 MB to 24 MB shared |
| Architecture and classification | |
| Technology node | 45 nm |
| Microarchitecture | Nehalem |
| Instruction set | x86-16, IA-32, x86-64 |
| Instructions | MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 |
| Extensions | |
| Products, models, variants | |
| Core names |
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| Product code name |
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| Models |
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| History | |
| Predecessors | Core (tock) Penryn (tick) |
| Successors | Westmere (tick) Sandy Bridge (tock) |
| Support status | |
| Unsupported | |
Nehalem /nəˈheɪləm/ is the codename for Intel's 45 nm microarchitecture released in November 2008. It was used in the first generation of the Intel Core i5 and i7 processors, and is a major evolution over the older Core microarchitecture, which is used by Core 2 processors and is the previous iteration of the P6 microarchitecture series which started in 1995 with the Pentium Pro. The term "Nehalem" comes from the Nehalem River.
Nehalem is built on the 45 nm process, is able to run at higher clock speeds without sacrificing efficiency, and is more energy-efficient than Penryn microprocessors. Hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores. Nehalem is an architecture that differs radically from NetBurst, while retaining some of the latter's minor features.
Nehalem later received a die-shrink to 32 nm with Westmere, and was fully succeeded by "second-generation" Sandy Bridge in January 2011.