P6 (microarchitecture)

P6
	Die shot of Deschutes core
General information
Launched	November 1, 1995
Performance
Max. CPU clock rate	150 MHz to 1.40 GHz
FSB speeds	66 MHz to 133 MHz
Physical specifications
Transistors	5.5M 500 nm; 7.5M 350 nm; 7.5M 250 nm (B0, B1); 9.5M 250 nm (B0, C0); 19M 250 nm (B0); 28M 180 nm (A1, A2, B0, C0, D0); 44M 130 nm (A1, B1, C1, D0);
Cores	1;
Sockets	Socket 8; Slot 1; Socket 370; Socket 479;
Cache
L1 cache	Pentium Pro: 16 KB (8 KB I cache + 8 KB D cache); Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache)
L2 cache	128 KB to 512 KB; 256 KB to 2048 KB (Xeon)
Architecture and classification
Microarchitecture	P6
Instruction set	x86-16, IA-32
Extensions	MMX (Pentium II/III/M); SSE (Pentium III/M); SSE2 (Pentium M);
Products, models, variants
Models	Pentium Pro Series; Celeron II Series; Pentium II Series; Pentium II Xeon Series; Celeron III Series; Pentium III Series; Pentium III Xeon Series;
History
Predecessor	P5
Successor	NetBurst
Support status
	Unsupported

The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, first implemented in the Pentium Pro microprocessor in 1995. It was partially succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, though it continued to be used in new processors through the mid-2000s. The Core microarchitecture, a derivative of the Enhanced Pentium M variant of P6, would later succeed both P6 and NetBurst.

P6 was used within Intel's mainstream offerings from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC).