Memory timings

Memory timings or RAM timings describe the timing information of a memory module or the onboard LPDDRx. Due to the inherent qualities of VLSI and microelectronics, memory chips require time to fully execute commands. Executing commands too quickly will result in data corruption and results in system instability. With appropriate time between commands, memory modules/chips can be given the opportunity to fully switch transistors, charge capacitors and correctly signal back information to the memory controller. Because system performance depends on how fast memory can be used, this timing directly affects the performance of the system.

The timing of modern synchronous dynamic random-access memory (SDRAM) is commonly indicated using four parameters: CL, T_RCD, T_RP, and T_RAS in units of clock cycles; they are commonly written as four numbers separated with hyphens, e.g. 7-8-8-24. Variations include:

The fourth (t_RAS) is often omitted.
Or a fifth, the Command rate, is sometimes added (normally 2T or 1T, also written 2N, 1N or CR2).

These parameters (as part of a larger whole) specify the clock latency of certain specific commands issued to a random access memory. Lower numbers imply a shorter wait between commands (as determined in clock cycles). The Intel systems also have Gear 2 (Gear type 0) and Gear 4 (Gear type 1).

Name	Symbol	Definition
CAS latency	CL	The number of cycles between sending a column address to the memory and the beginning of the data in response. This is the number of cycles it takes to read the first bit of memory from a DRAM with the correct row already open. Unlike the other numbers, this is not a minimum, but an exact number that must be agreed on between the memory controller and the memory.
Row Address to Column Address Delay	T_RCD	The minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is T_RCD + CL. Some memory controllers break this down into two values, T_RCDwr (write) and T_RCDrd (read).
Row Precharge Time	T_RP	The minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is T_RP + T_RCD + CL.
Row Active Time	T_RAS	The minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with T_RCD. In SDRAM modules, it is simply T_RCD + CL. Otherwise, approximately equal to T_RCD + 2×CL.
Notes: RAS : Row Address Strobe, a terminology holdover from asynchronous DRAM. CAS : Column Address Strobe, a terminology holdover from asynchronous DRAM. T_WR : Write Recovery Time, the time that must elapse between the last write command to a row and precharging it. Generally, T_RAS ≈ T_RCD + T_WR. T_RC : Row Cycle Time. T_RC ≥ T_RAS + T_RP.

What determines absolute latency (and thus system performance) is determined by both the timings and the memory clock frequency. When translating memory timings into actual latency, timings are in units of clock cycles, which for double data rate memory is half the speed of the commonly quoted transfer rate. Without knowing the clock frequency it is impossible to state if one set of timings is "faster" than another.

For example, DDR3-2000 memory has a 1000 MHz clock frequency, which yields a 1 ns clock cycle. With this 1 ns clock, a CAS latency of 7 gives an absolute CAS latency of 7 ns. Faster DDR3-2666 memory (with a 1333 MHz clock, or 0.75 ns exactly; the 1333 is rounded) may have a larger CAS latency of 9, but at a clock frequency of 1333 MHz the amount of time to wait 9 clock cycles is only 6.75 ns. It is for this reason that DDR3-2666 CL9 has a smaller absolute CAS latency than DDR3-2000 CL7 memory.